1. Field of the Invention
The present invention relates to a variable delay circuit for varying delay time and pulse width in a semiconductor integrated circuit.
2. Description of the Prior Art
Since the frequencies used in recent semiconductor integrated circuits have risen, the standard data set-up time and hold time, which are set for reading out data, for example, a set-up time 2.5 ns and hold time 0.5 ns being required for 200 MHz, in response to a clock signal has become more strict. The set-up time and the hold time are defined as periods which are set in relation to a clock signal to read out data in a flip-flop. During this set-up time, the input data must exist at an input of the flip-flop before the clock rises. During the hold time, the data must also exist at an input of the flip-flop after the clock has risen. In order for the input data to be read out correctly, the data must exist at the input of the flip-flop during these periods. In order to satisfy this requirement, a delay buffer is provided before the input terminal of the flip-flop in a conventional device for adjusting the data set-up time and the hold time.
FIG. 24 shows a conventional variable delay circuit disclosed in the Japanese laid-open patent publication 63-9220. The circuit of FIG. 24 comprises a terminal 41 for supplying power, an input terminal 42 for receiving data, an output terminal 43 for outputting delayed data, control terminals 44-47 for controlling the data delay time, four P channel MOS transistors 48 connected in parallel, four N channel MOS transistors 49 connected in parallel, decoders 50 and 51 for decoding the control signals input from the control terminals 44-47, and selectors 52 and 53 for controlling the gates of the P channel MOS transistors 48 and the gates of the N channel MOS transistors 49 based on the output signal decoded in the decoders 50 and 51.
The operation of the circuit illustrated in FIG. 24 is explained below. The control signals are input to the control terminals 44-47 and decoded by the decoders 50 and 51. The decoded signals turn on and off an arbitrary number of the P channel MOS transistors 48 or the N channel MOS transistors 49. The more transistors operating in parallel, the shorter the delay time, and the fewer transistors operating in parallel, the longer the delay time. This means that it is possible to vary the delay time by controlling the number of operating transistors, which are connected in parallel, using the control signals. A desired set-up time or hold time has been achieved in this manner.
FIG. 25 shows a conventional variable pulse width circuit that is commonly used. The circuit of FIG. 25 comprises a data input terminal 31, a data output terminal 37, unit delaying elements 32-35, and an AND circuit 36 for logically summing the data signals from the input terminal 31 and the signal delayed by the delay elements 32-35. FIGS. 26A-26F are timing charts illustrating how a data signal is delayed. In FIGS. 26A-26F, DATA IN, A, B, C, D, and OUT indicate the waveforms of signals at the locations of the corresponding reference symbols in the circuit of FIG. 25. As shown in FIG. 26A, the data signal is input to the input terminal 31, and sequentially delayed in the respective delaying elements, and the AND circuit 36 logically sums up the output (the waveform at D) of the delaying element 35 and the input signal from the data input terminal 31 (the waveform at DATA IN) to obtain the waveform shown in FIG. 26F. This waveform at OUT (FIG. 26F) is output as the input waveform (FIG. 26A) with a delay of time period .tau.. In this manner, the circuit shown in FIG. 25 is used to vary a pulse width.
However, since the respective gate widths of the P channel MOS transistors 48 and N channel MOS transistors 49 are constant, the circuit of FIG. 24 cannot control a minute delay time shorter than a predetermined length, which is determined by the unit transistor. For this reason, it has been difficult to adjust the desired set-up time and the hold time minutely.
Moreover, the variable pulse width circuit shown in FIG. 25 could not control a minute delay time shorter than a predetermined length, which is determined by the unit delay element. The present invention is created to solve these problems.